1. Field of the Invention
The present invention relates to a memory module and, in particular, to a memory module on which memory chips are arranged in a space-saving manner. In addition, the present invention relates to a memory chip suited for such a memory module.
2. Description of the Prior Art
A top view and a side view of a prior art memory module are shown in FIGS. 11a and 11b. 
The memory module comprises a memory module board 10, memory chips 12 located on a first main surface of the memory module board 10 and memory chips 14 arranged on a second main surface of the memory module board which is opposite to the first main surface. Circuitry for controlling the operation of the memory chips 12 and 14, such as a PLL 16 (PLL=phase locked loop) and command address registers 18 are provided on the memory module board 10. Comparable circuitry can be formed on the back side of the memory module board not shown in FIG. 11a. The memory controller is usually arranged on a motherboard having a plug-in connector into which the memory module shown in FIGS. 11a and 11b is plugged such that terminals 20 of an edge connector of the memory module board 10 are connected to mating terminals in the plug-in connector. In addition, a memory controller can be provided on the motherboard. For the sake of clarity, respective conductive traces connecting the elements of the memory module to each other are not shown in FIGS. 11a and 11b. 
As can be seen in FIG. 11a, four memory chips, DRAMs in the memory module shown, are arranged on both, the top side and the back side of the module board on the left of the circuitry 16, 18, and five memory chips are arranged on both, the top side and the back side of the memory module board 10, on the right of the circuitry 16, 18. Thus, in total, eight memory chips are located on the left of the circuitry 16, 18 and ten memory chips are located on the right thereof. Thus, only a limited number of eighteen DRAMs can be placed on a memory module of a given size using existing stacking technology.
In order to reduce the space requirements of memories, one prior art approach is to stack DRAM chips on a module board onto each other. A further prior art approach is to stack respective module boards onto each other or to provide a foldable electronic memory module assembly as available from KentronR Technologies under the product name FEMMA™.
U.S. Pat. No. B1-6,480,014 relates to high density, high frequency memory chip modules wherein a respective memory chip is mounted to a daughter board. The daughter board is provided with a plurality of pins along one edge thereof. The pins are inserted into matching holes provided in a module board and soldered thereto. When mounted to the module board, the daughter boards and the memory chips mounted thereto are oriented vertical or inclined with respect to the module board. Moreover, heat spreaders can be provided on the respective daughter boards.